1. Field of the Invention
The present invention relates to a DC converter with high efficiency and low noise.
2. Description of the Related Art
FIG. 1 shows a DC converter according to a related art. The DC converter of FIG. 1 employs an active clamp method and includes a DC power source Vin, a transformer T having a primary winding P1 (the number of turns is n1) connected to the DC power source Vin, and a main switch Q1 connected to the primary winding P1. The main switch Q1 is a MOSFET (hereinafter referred to as “FET”). Ends of the primary winding P1 are connected to a series circuit consisting of an auxiliary switch Q2 and a clamp capacitor C2. The auxiliary switch Q2 is a FET. The main switch Q1 and auxiliary switch Q2 have a dead time in which both of them are OFF. The switches Q1 and Q2 are alternately turned on/off under PWM control conducted by a controller 111.
The transformer T has the primary winding P1 and a secondary winding S1 (the number of turns is n2) that are wound to generate in-phase voltages. The secondary winding S1 is connected to a rectifying/smoothing circuit including diodes D10 and D11, a reactor L10, and a capacitor C10. The rectifying/smoothing circuit rectifies and smoothes a voltage (on/off-controlled pulse voltage) induced on the secondary winding S1 of the transformer T and provides a DC output to a load 30.
Based on the output voltage to the load 30, the controller 111 generates a control pulse signal to turn on/off the main switch Q1 and auxiliary switch Q2. In addition, the controller 111 controls the duty factor of the control signal so that the output voltage maintains a predetermined value.
The DC converter further includes an inverter 112, a bottom detector 113, a first delay circuit 114, and a second delay circuit 115.
The inverter 112 inverts a Q1 control signal Q1c, which is supplied from the controller 111 to control the main switch Q1, into a Q2 control signal Q2c and supplies it to the second delay circuit 115. The bottom detector 113 detects a minimum voltage (bottom voltage) of the main switch Q1 after the auxiliary switch Q2 turns off and provides a bottom detection signal Btm indicative of the bottom voltage.
The first delay circuit 114 delays a rise of the Q1 control signal Q1c from the controller 111 until a rise of the bottom detection signal Btm from the bottom detector 113, to generate a Q1 gate signal Q1g, which is applied to the gate of the main switch Q1 to drive the main switch Q1. The second delay circuit 115 delays a rise of the Q2 control signal Q2c from the inverter 112 by a predetermined time, to generate a Q2 gate signal Q2g and applies it to the gate of the auxiliary switch Q2, thereby driving the auxiliary switch Q2.
Operation of the DC converter with the above-mentioned configuration will be explained with reference to a timing chart of FIG. 2. In FIG. 2, a voltage Q1v is a drain-source voltage of the main switch Q1.
At t30, the Q1 control signal Q1c from the controller 111 rises to a high level, and the Q2 control signal Q2c falls to a low level. As a result, the Q2 gate signal Q2g becomes low to turn off the auxiliary switch Q2. The bottom detection signal Btm is low at t30.
After the auxiliary switch Q2 is turned off, the voltage Q1v of the main switch Q1 decreases. At t31, the bottom detector 113 detects a minimum (bottom) of the voltage Q1v. As a result, the bottom detection signal Btm from the bottom detector 113 becomes high, and after a vary short period of time, becomes low.
At t32, the first delay circuit 114 raises the Q1 gate signal Q1g to high to turn on the main switch Q1, thereby achieving bottom-voltage switching, or zero-volt switching of the main switch Q1.
When the main switch Q1 is turned on, a current from the DC power source Vin passes through the primary winding P1 of the transformer T and the main switch Q1. At this time, the rectifying/smoothing circuit passes a current through a route of S1, D10, L10, C10, and S1.
At t33, the Q1 control signal Q1c falls to turn off the main switch Q1. Energy accumulated in the primary winding P1 of the transformer T and in a leakage inductance between the primary and secondary windings of the transformer T charges a parasitic capacitor (not shown) of the main switch Q1, to produce a voltage resonance. As a result, the voltage Q1v of the main switch Q1 increases during a period from t33 to t34. The rectifying/smoothing circuit passes a current through a route of L10, C10, D11, and L10 to supply the current to the load 30.
At t34, the Q2 gate signal Q2g rises to turn on the auxiliary switch Q2. Energy accumulated in the primary winding P1 of the transformer T is supplied to the clamp capacitor C2 to charge the clamp capacitor C2. Energy accumulated in the clamp capacitor C2 passes through a route of C2, Q2, P1, and C2.